Publications

Qiang Xu

Department of Computer Science & Engineering
The Chinese University of Hong Kong
Shatin, N.T., Hong Kong

Email:
Phone:
Fax:
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qxu AT cse.cuhk.edu.hk
+852.3943.8436
+852.2603.5024
Room 1008, Ho Sin Hang Building

Professional Activities

Vacancy

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Referred Conference Papers

[C98] J. Yi, Q. Zhang, Y. Tian, T. Wang, W. Liu, E. H.-M. Sha, and Q. Xu, "ApproxMap: On Task Allocation and Scheduling for Resilient Applications", accepted for publication in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2016. (acceptance rate: 94/274 = 34.3%)

[C97] Q. Zhang, Y. Tian, T. Wang, F. Yuan, and Q. Xu, "ApproxEigen: An Approximate Computing Technique for Large-Scale Eigen-Decomposition", accepted for publication in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2015.

[C96] L. Wei, C. Song, Y. Liu, J. Zhang, F. Yuan, and Q. Xu, "BoardPUF: Physical Unclonable Functions for Printed Circuit Board Authentication", accepted for publication in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2015.

[C95] L. Jiang, X. Huang, H. Xie, Q. Xu, C. Li, X. Liang, and H. Li, "A Novel TSV Probing Technique with Adhesive Test Interposer", accepted for publication in Proc. IEEE International Conference on Computer Design (ICCD), Oct. 2015.

[C94] L. Jiang, P. Pang, N. Jing, X. Liang, and Q. Xu, "On Diagnosable and Tunable 3D Clock Network Design for Lifetime Reliability Enhancement", accepted for publication in Proc. IEEE International Test Conference (ITC), Sept. 2015.

[C93] S. Yao, X. Chen, J. Zhang, Q. Liu, J. Wang, Q. Xu, Y. Wang, and H. Yang, "FASTrust: Feature Analysis for Third-Party IP Trust Verification", accepted for publication in Proc. IEEE International Test Conference (ITC), Sept. 2015.

[C92] L. Jiang and Q. Xu, "Fault-Tolerant 3D NoC Architecture and Design: Recent Advances and Challenges", to appear in Proc. International Symposium on Networks-on-Chip (NOCS), Sept. 2015. (invited paper)

[C91] Y. Liu, J. Zhang, L. Wei, F. Yuan and Q. Xu, "DERA: Yet Another Differential Fault Attack on Cryptographic Devices Based on Error Rate Analysis", accepted for publication in Proc. ACM/IEEE Design Automation Conference (DAC), June 2015. (Nominated for Best Paper Award, acceptance rate: 162/789 = 20.5%)

[C90] F. Xie, X. Liang, Q. Xu, K. Chakrabarty, N. Jing and L. Jiang, "Jump Test for Metallic CNTs in CNFET-Based SRAM", accepted for publication in Proc. ACM/IEEE Design Automation Conference (DAC), June 2015. (acceptance rate: 162/789 = 20.5%)

[C89] Y. Tian, Q. Zhang, T. Wang, F. Yuan and Q. Xu, "ApproxMA: Approximate Memory Access for Dynamic Precision Scaling", to appear in Proc. Great Lakes Symposium on VLSI (GLVLSI), May 2015. (invited paper)

[C88] Q. Han, J. Guo, Q. Xu, and W.-B. Jone, "On Resilient System Performance Binning", accepted for publication in Proc. ACM International Symposium on Physical Design (ISPD), Mar. 2015.

[C87] Q. Zhang, T. Wang, Y. Tian, F. Yuan and Q. Xu, "ApproxANN: An Approximate Computing Framework for Artificial Neural Network", accepted for publication in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Mar. 2015. (acceptance rate: 205/915 = 22.4%)

[C86] R. Ye, F. Yuan, J. Zhang and Q. Xu, "On the Premises and Prospects of Timing Speculation", accepted for publication in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Mar. 2015. (interactive presentation, acceptance rate: (205+86)/915 = 31.8%)

[C85] L. Wei, J. Zhang, F. Yuan, Y. Liu, J. Fan, and Q. Xu, "Vulnerability Analysis for Crypto Devices against Probing Attack", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 827-832, Jan. 2015. (acceptance rate: 108/318 = 33.9%)

[C84] Z. Sun, L. Jiang, Q. Xu, Z. Zhang，Z. Wang, and X. Gu, "On Test Syndrome Merging for Reasoning-Based Board-Level Functional Fault Diagnosis", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 737-742, Jan. 2015. (acceptance rate: 108/318 = 33.9%)

[C83] J. Zhang, F. Yuan, and Q. Xu, "DeTrust: Defeating Hardware Trust Verification with Stealthy Implicitly-Triggered Hardware Trojans", Proc. ACM Conference on Computer and Communications Security (CCS), pp. 153-166, Nov. 2014. (acceptance rate: 114/585 = 19.5%)

[C82] J. Zhang, G. Su, Y. Liu, L. Wei, F. Yuan, G. Bai, and Q. Xu, "On Trojan Side Channel Design and Identification", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 278-285, Nov. 2014.

[C81] Q. Zhang, F. Yuan, R. Ye and Q. Xu, "ApproxIt: An Approximate Computing Framework for Iterative Methods", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 1-6, June 2014. (acceptance rate: 174/787 = 22.1%)

[C80] T. Wang and Q. Xu, "On the Simulation of NBTI-Induced Performance Degradation Considering Arbitrary Temperature and Voltage Variations", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 1-6, June 2014. (acceptance rate: 174/787 = 22.1%)

[C79] R. Ye, T. Wang, F. Yuan, R. Kumar and Q. Xu, "On Reconfiguration-Oriented Approximate Adder Design and Its Application", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 48-54, Nov. 2013. (acceptance rate: 92/354 = 26.0%)

[C78] J. Zhang, F. Yuan, R. Ye, and Q. Xu, "ForTER: A Forward Error Correction Scheme for Timing Error Resilience", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 55-60, Nov. 2013. (acceptance rate: 92/354 = 26.0%)

[C77] Z. Sun, L. Jiang, Q. Xu, Z. Zhang，Z. Wang, and X. Gu, "AgentDiag: An Agent-Assisted Diagnostic Framework for Board-Level Functional Failures", Proc. IEEE International Test Conference (ITC), paper 11.2, Sept. 2013.

[C76] J. Zhang, F. Yuan, L. Wei, Z. Sun, and Q. Xu, "VeriTrust: Verification for Hardware Trust", Proc. ACM/IEEE Design Automation Conference (DAC), No. 61, June 2013. (acceptance rate: 162/747 = 21.7%)

[C75] F. Yuan and Q. Xu, "InTimeFix: A Low Cost and Scalable Technique for In-Situ Timing Error Masking in Logic Circuits", Proc. ACM/IEEE Design Automation Conference (DAC), No. 183, June 2013. (acceptance rate: 162/747 = 21.7%)

[C74] L. Jiang, Q. Xu, F. Ye, K. Chakrabarty, and B. Eklow, "On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs", Proc. ACM/IEEE Design Automation Conference (DAC), No. 74, June 2013. (acceptance rate: 162/747 = 21.7%)

[C73] F. Yuan, Y. Liu, W.-B. Jone, and Q. Xu, "On Testing Timing-Speculative Circuits", Proc. ACM/IEEE Design Automation Conference (DAC), No. 30, June 2013. (acceptance rate: 162/747 = 21.7%)

[C72] R. Ye, F. Yuan, Z. Sun, W.-B. Jone, and Q. Xu, "Post-Placement Voltage Island Generation for Timing-Speculative Circuits", Proc. ACM/IEEE Design Automation Conference (DAC), No. 112, June 2013. (acceptance rate: 162/747 = 21.7%)

[C71] J. Zhang and Q. Xu, "On Hardware Trojan Design and Implementation at RTL", Proc. IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 107-112, June 2013. (acceptance rate: 19/64 = 29.7%)

[C70] Y. Liu, R. Ye, F. Yuan and Q. Xu, "Optimization for Timing-Speculated Circuits by Redundancy Addition and Removal", Proc. IEEE European Test Symposium (ETS), pp. 1-6, May 2013.

[C69] Y. Han, S. Jin, J. Qiu, Q. Xu, and X. Li, "On Predicting NBTI-Induced Circuit Aging by Isolating Leakage Change", Proc. International Symposium on Quality Electronic Design (ISQED), pp. 46-52, Mar. 2013

[C68] Y. Liu, R. Ye, F. Yuan, R. Kumar and Q. Xu, "On Logic Synthesis for Timing Speculation", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 591-596, Nov. 2012. (acceptance rate: 82/338 = 24.3%)

[C67] X. Liu and Q. Xu, "On Efficient Silicon Debug with Flexible and X-Tolerant Trace Interconnection Fabric", Proc. IEEE International Test Conference (ITC), paper 3.1, Nov. 2012.

[C66] Y. Liu and Q. Xu, "On Modeling Faults in FinFET Logic Circuits", Proc. IEEE International Test Conference (ITC), paper 11.3, Nov. 2012.

[C65] J. Zhang, H. Yu and Q. Xu, "HTOutlier: Hardware Trojan Detection with Side-Channel Signature Outlier Identification", Proc. IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 55-58, June 2012.

[C64] F. Yuan, X. Liu and Q. Xu, "X-Tracer: A Reconfigurable X-Tolerant Trace Compressor for Silicon Debug", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 555-560, June 2012. (acceptance rate: 164/741 = 22.1%)

[C63] L. Jiang, Q. Xu, and B. Eklow, "On Effective TSV Repair for 3D-Stacked ICs", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 793-798, Mar. 2012.

[C62] R. Ye, F. Yuan, H. Zhou and Q. Xu, "Clock Skew Scheduling for Timing Speculation", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 929-934, Mar. 2012.

[C61] Q. Xu, L. Jiang, H. Li, and B. Eklow, "Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 731-737, Jan. 2012. (invited paper)

[C60] R. Ye and Q. Xu, "Learning-Based Power Management for Multi-Core Processors via Idle Period Manipulation", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 115-120, Jan. 2012. (Nominated for Best Paper Award, acceptance rate: 99/288 = 34.4%)

[C59] Y. Zhang, H. Yu and Q. Xu, "CODA: A Concurrent Online Delay Measurement Architecture for Critical Paths", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 169-174, Jan. 2012. (acceptance rate: 99/288 = 34.4%)

[C58] F. Yuan, X. Liu and Q. Xu, "Pseudo-Functional Testing for Small Delay Defects Considering Power Supply Noise Effects", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 34-39, Nov. 2011. (acceptance rate: 106/349 = 30.4%)

[C57] R. Ye, F. Yuan and Q. Xu, "Online Clock Skew Tuning for Timing Speculation", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 442-227, Nov. 2011. (acceptance rate: 106/349 = 30.4%)

[C56] P. Marwedel, J. Teich, G. Kouveli, L. Bacivarov, L. Thiele, S. Ha, C. Lee, Q. Xu, and L. Huang, "Mapping of Applications to MPSoCs", Proc. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 109-118, Oct. 2011.

[C55] H. Yu, Q. Xu and P. H. W. Leong, "On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry", Proc. International Conference on Field-Programmable Logic and Applications (FPL), pp 539-544, Sept. 2011.

[C54] Y. Liu, F. Yuan and Q. Xu, "Re-Synthesis for Cost-Efficient Circuit-Level Timing Speculation", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 158-163, June 2011. (acceptance rate: 156/690 = 22.6%)

[C53] L. Huang, R. Ye and Q. Xu, "Customer-Aware Task Allocation and Scheduling for Multi-Mode MPSoCs", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 387-392, June 2011. (acceptance rate: 156/690 = 22.6%)

[C52] X. Liu and Q. Xu, "On Multiplexed Signal Tracing for Post-Silicon Debug", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1-6, March 2011.

[C51] J. Li, Q. Xu and D. Xiang, "Compression-Aware Capture Power Reduction for At-Speed Testing", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 806-811, Jan. 2011.

[C50] H. Yu, Q. Xu and P. H. W. Leong, "Fine-Grained Characterization of Process Variation in FPGAs", accepted for publication in Proc. IEEE International Conference on Field-Programmable Technology (FPT), pp. 138-145, Dec. 2010. (acceptance rate: 37/166 = 22.3%)

[C49] H. Yu, P. H. W. Leong and Q. Xu, "An FPGA Chip Identification Generator Using Configurable Ring Oscillator", Proc. IEEE International Conference on Field-Programmable Technology (FPT), pp. 312-315, Dec. 2010. (acceptance rate: 37+46/166 = 50.0%)

[C48] X. Liu and Q. Xu, "On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation", Proc. IEEE Asian Test Symposium (ATS), pp. 243-248, Dec. 2010.

[C47] L. Jiang, R. Ye and Q. Xu, "Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing across Dies", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 230-234, Nov. 2010. (Nominated for Best Paper Award, acceptance rate: 108/360 = 30.0%)

[C46] F. Yuan and Q. Xu, "On Timing-Independent False Path Identification", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 532-535, Nov. 2010. (acceptance rate: 108/360 = 30.0%)

[C45] L. Huang and Q. Xu, "Characterizing the Lifetime Reliability of Manycore Processors with Core-Level Redundancy", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 680-685, Nov. 2010. (Nominated for Best Paper Award, acceptance rate: 108/360 = 30.0%)

[C44] L. Jiang, Y. Liu, L. Duan, Y. Xie and Q. Xu, "Modeling TSV Open Defects in 3D-Stacked DRAM", Proc. IEEE International Test Conference (ITC), paper 6.1, Nov. 2010.

[C43] L. Huang and Q. Xu, "Performance Yield-Driven Task Allocation and Scheduling for MPSoCs under Process Variation", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 326-331, June 2010. (acceptance rate: 148/607 = 24.4%)

[C42] L. Huang and Q. Xu, "AgeSim: A Simulation Framework for Evaluating the Lifetime Reliability of Processor-Based SoCs", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 51-56, March 2010. (Nominated for Best Paper Award, acceptance rate: ~25%)

[C41] L. Huang and Q. Xu, "Energy-Efficient Task Allocation and Scheduling for Multi-Mode MPSoCs under Lifetime Reliability Constraint", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1584-1589, March 2010. (acceptance rate: ~25%)

[C40] X. Liu, Y. Zhang, F. Yuan and Q. Xu, "Layout-Aware Pseudo-Functional Testing for Critical Paths Considering Power Supply Noise Effects", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1432-1437, March 2010. (acceptance rate: ~25%)

[C39] Q. Xu and X. Liu, "On Signal Tracing in Post-Silicon Validation", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 262-267, Jan. 2010. (invited paper)

[C38] L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak, "Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 191-196, Nov. 2009. (acceptance rate: 115/438 = 26.3%)

[C37] Y. Zhang, L. Huang, F. Yuan and Q. Xu, "Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks", Proc. IEEE Asian Test Symposium (ATS), pp. 460-465, Nov. 2009.

[C36] F. Yuan and Q. Xu, "Compression-Aware Pseudo-Functional Testing", Proc. IEEE International Test Conference (ITC), paper 9.1, Nov. 2009.

[C35] L. Huang and Q. Xu, "Test Economics for Homogeneous Manycore Systems", Proc. IEEE International Test Conference (ITC), paper 12.3, Nov. 2009.

[C34] X. Liu and Q. Xu, "On Simultaneous Shift- and Capture-Power Reduction in Linear Decompressor-Based Test Compression Environment", Proc. IEEE International Test Conference (ITC), paper 9.3, Nov. 2009.

[C33] F. Yuan and Q. Xu, "On Systematic Illegal State Identification for Pseudo-Functional Testing", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 702-707, July 2009. (acceptance rate: 148/682 = 21.7%)

[C32] X. Liu and Q. Xu, "Interconnection Fabric Design for Tracing Signals in Post-Silicon Validation", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 352-357, July 2009. (acceptance rate: 148/682 = 21.7%)

[C31] L. Huang, F. Yuan and Q. Xu, "Lifetime Reliability-Aware Task Allocation and Scheduling for MPSoC Platforms", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 51-56, Apr. 2009. (acceptance rate: 226/965 = 23.4%)

[C30] L. Jiang, L. Huang and Q. Xu, "Test Architecture Design and Optimization for Three-Dimensional SoCs", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 220-225, Apr. 2009. (acceptance rate: 226/965 = 23.4%)

[C29] X. Liu and Q. Xu, "Trace Signal Selection for Visibility Enhancement in Post-Silicon Validation", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1338-1343, Apr. 2009. (acceptance rate: 226/965 = 23.4%)

[C28] X. Liu and Q. Xu, "A Generic Framework for Scan Capture Power Reduction in Fixed-Length Symbol-based Test Compression Environment", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1494-1499, Apr. 2009. (acceptance rate: 226/965 = 23.4%)

[C27] L. Huang and Q. Xu, "On Modeling the Lifetime Reliability of Homogeneous Manycore Systems", Proc. IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), pp. 87-94, Dec. 2008.

[C26] X. Liu and Q. Xu, "On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation", Proc. IEEE Asian Test Symposium (ATS), pp. 303-308, Nov. 2008.

[C25] J. Li, X. Liu, Y. Zhang, Y. Hu, X. Li and Q. Xu, "On Capture Power-Aware Test Data Compression for Scan-Based Testing", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 67-72, Nov. 2008. (acceptance rate: 122/458 = 26.6%)

[C24] F. Yuan and Q. Xu, "SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects", Proc. IEEE International Test Conference (ITC), paper 26.2, Oct. 2008.

[C23] L. Huang, F. Yuan, and Q. Xu, "On Reliable Modular Testing with Vulnerable Test Access Mechanisms", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 834-839, June 2008. (acceptance rate: 147/639 = 23.0%)

[C22] S. Tang and Q. Xu, "In-band Cross-Trigger Event Transmission for Transaction-Based Debug", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 414-419, Mar. 2008. (acceptance rate: 198/837 = 23.7%)

[C21] F. Yuan, L. Huang and Q. Xu, "Re-Examining the Use of Network-on-Chip as Test Access Mechanism", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 808-811, Mar. 2008. (interactive presentation, acceptance rate: (198+46)/837 = 29.2%)

[C20] J. Li, Q. Xu, Y. Hu and X. Li, "iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1184-1189, Mar. 2008. (acceptance rate: 198/837 = 23.7%)

[C19] L. Zhang, Y. Han, Q. Xu and X. Li, "Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 891-896, Mar. 2008. (acceptance rate: 198/837 = 23.7%)

[C18] J. Li, Q. Xu, Y. Hu and X. Li, "Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction", Proc. IEEE International Symposium on Electronic Design, Test & Applications (DELTA), pp. 26-31, Jan. 2008.

[C17] S. Tang and Q. Xu, "A Debug Probe for Concurrently Debugging Multiple Embedded Cores and Inter-Core Transactions in NoC-Based Systems", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 416-421, Jan. 2008. (acceptance rate: 100/350 = 28.5%)

[C16] J. Li, Q. Xu, Y. Hu and X. Li, "On Reducing Both Shift and Capture Power for Scan-Based Testing", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 653-658, Jan. 2008. (short paper, acceptance rate: (100+23)/350 = 35.1%)

[C15] Q. Xu, Y. Zhang and K. Chakrabarty, "Test-Wrapper Designs for the Detection of Signal-Integrity Faults on Core-External Interconnects of SoCs", Proc. IEEE International Test Conference (ITC), paper 5.1, Oct. 2007.

[C14] Q. Xu, D. Hu and D. Xiang, "Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction", Proc. IEEE International Test Conference (ITC), paper 25.2, Oct. 2007.

[C13] Q. Xu, Y. Zhang and K. Chakrabarty, "SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 676-681, June, 2007. (acceptance rate: 152/659 = 23.1%)

[C12] S. Tang and Q. Xu, "A Multi-Core Debug Platform for NoC-Based Systems", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 870-875, Apr. 2007. (acceptance rate: 208/933 = 22.3%)

[C11] B. Wang and Q. Xu, "Test/Repair Area Overhead Reduction for Small Embedded SRAMs", Proc. IEEE Asian Test Symposium (ATS), pp. 37-44, Nov. 2006.

[C10] Q. Xu, B. Wang and F. Y. Young, "Retention-Aware Test Scheduling for BISTed Embedded SRAMs", Proc. IEEE European Test Symposium (ETS), pp. 83-88, May 2006. (acceptance rate: 35/198 = 17.7%)

[C9] Q. Xu and N. Nicolici, "On Concurrent Test of Wrapped Cores and Unwrapped Logic Blocks in SOCs", Proc. IEEE International Test Conference (ITC), paper 25.2, Oct. 2005.

[C8] Q. Xu, N. Nicolici and K. Chakrabarty, "Multi-Frequency Wrapper Design and Optimization for Embedded Cores under Average Power Constraints", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 123-128, June, 2005. (acceptance rate: 154/735 = 21.0%)

[C7] H. Ko, Q. Xu and N. Nicolici, "Register-Transfer Level Functional Scan for Hierarchical Designs", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1172-1175, Jan. 2005. (short paper, acceptance rate: (99+86)/692 = 26.7%)

[C6] Q. Xu and N. Nicolici, "Multi-frequency Test Access Mechanism Design for Modular SOC Testing", Proc. IEEE Asian Test Symposium (ATS), pp. 2-7, Nov. 2004.

[C5] Q. Xu and N. Nicolici, "Time/Area Tradeoffs in Testing Hierarchical SOCs with Hard Mega-Cores", Proc. IEEE International Test Conference (ITC), pp. 1196-1202, Oct. 2004.

[C4] Q. Xu and N. Nicolici, "Wrapper Design for Testing IP Cores with Multiple Clock Domains", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 416-421, Feb. 2004. (Best Paper Award, 3 out of 780, acceptance rate: 181/780 = 23.2%)

[C3] B. Fang, Q. Xu and N. Nicolici, "Hardware/Software Co-testing of Embedded Memories in Complex SOC", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 599-605, Nov. 2003. (acceptance rate: 129/490 = 26.3%)

[C2] Q. Xu and N. Nicolici, "On Reducing Wrapper Boundary Register Cells in Modular SOC Testing", Proc. IEEE International Test Conference (ITC), pp. 622-631, Oct. 2003.

[C1] Q. Xu and N. Nicolici, "Delay Fault Testing of Core-Based Systems-on-a-Chip", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 744-749, Mar. 2003. (acceptance rate: 152/590 = 25.8%)

Referred Journal Articles

[J23] X. Liu and Q. Xu, "On Multiplexed Signal Tracing for Post-Silicon Validation", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[J22] L. Jiang, Q. Xu, and B. Eklow, "On Effective TSV Repair for 3D-Stacked ICs", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[J21] X. Liu and Q. Xu, "On X-Variable Filling and Flipping for Capture Power Reduction in Linear Decompressor-Based Test Compression Environment", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[J20] X. Liu and Q. Xu, "On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[J19] H. Yu, P. H. W. Leong and Q. Xu, "An FPGA Chip Identification Generator Using Configurable Ring Oscillator", accepted for publication in IEEE Transactions on VLSI Systems.

[J18] L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak, "Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3D SoCs under Pre-Bond Test-Pin-Count Constraint", accepted for publication in IEEE Transactions on VLSI Systems.

[J17] L. Huang, F. Yuan, and Q. Xu, "On Task Allocation and Scheduling for Lifetime Extension of Platform-Based MPSoC Designs", IEEE Transactions on Parallel and Distributed Systems, vol 22, pp. 2088-2099, Dec. 2011.

[J16] J. Li, X. Liu, Y. Zhang, Y. Hu, X. Li, and Q. Xu, "Capture-Power-Aware Test Data Compression Using Selective Encoding", Integration, the VLSI Journal, vol. 44, pp. 205-216, June 2011.

[J15] L. Huang and Q. Xu, "Economic Analysis of Testing Homogeneous Manycore Chips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1257-1270, Aug. 2010.

[J14] J. Li, Q. Xu, Y. Hu and X. Li, "X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing", IEEE Transactions on VLSI Systems, vol. 18, pp. 1081-1092, July 2010.

[J13] L. Huang and Q. Xu, "Lifetime Reliability for Load-Sharing Redundant Systems with Arbitrary Failure Distributions", IEEE Transactions on Reliability, vol. 50, pp. 319-330, June 2010.

[J12] L. Zhang, Y. Han, Q. Xu, X. Li and H. Li, "On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems", IEEE Transactions on VLSI Systems, vol. 17, pp. 1173-1186, Sept. 2009.

[J11] D. Xiang, D. Hu, Q. Xu and A. Orailoglu, "Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 28, pp. 1101-1105, July 2009.

[J10] Q. Xu, Y. Zhang and K. Chakrabarty, "SOC Test-Architecture Optimization for the Testing of Embedded Cores and Signal-Integrity Faults on Core-External Interconnects", ACM Transactions on Design Automation of Electronic Systems, vol. 14, article No. 4, Jan. 2009.

[J9] J.-L. Yang and Q. Xu, "State-Sensitive X-Filling Scheme for Scan Capture Power Reduction", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 27, pp. 1338-1343, July 2008.

[J8] Q. Xu, N. Nicolici and K. Chakrabarty, "Test Wrapper Design and Optimization under Power Constraints for Embedded Cores with Multiple Clock Domain", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 26, pp. 1539-1547, Aug. 2007.

[J7] Q. Xu, B. Wang, A. Ivanov and F. Y. Young, "Test Scheduling for BISTed Embedded SRAMs with Data Retention Faults", IEE Proceedings: Computers and Digital Techniques (Special Issue on ETS'06), vol. 1, pp. 256-264, May 2007.

[J6] Q. Xu and N. Nicolici, "DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs", IEEE Transactions on Computers, vol. 55, pp. 470-485, Apr. 2006.

[J5] Q. Xu and N. Nicolici, "Multi-Frequency TAM Design for Hierarchical SOCs", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 25, pp. 181-196, Jan. 2006.

[J4] Q. Xu and N. Nicolici, "Modular SOC Testing with Reduced Wrapper Count", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 24, pp. 1894-1908, Dec. 2005.

[J3] Q. Xu and N. Nicolici, "Modular and Rapid Testing of SOCs with Unwrapped Logic Blocks", IEEE Transactions on VLSI Systems, vol. 13, pp. 1275-1285, Nov. 2005.

[J2] Q. Xu and N. Nicolici, "Wrapper Design for Multi-Frequency IP Cores", IEEE Transactions on VLSI Systems, vol. 13, pp. 678-685, June, 2005.

[J1] Q. Xu and N. Nicolici, "Resource-Constrained System-on-a-Chip Test: A Survey", IEE Proceedings: Computers and Digital Techniques. vol. 152, pp. 67-81, Jan. 2005.

Books and Book Chapters

[B1] X. Liu and Q. Xu, "Trace-Based Post-Silicon Validation for VLSI Circuits", Lecture Notes in Electrical Engineering 252, Springer 2014, ISBN 978-3-319-00532-4.

Others

唐杉，徐強，王莉, "数字IC设计--方法技巧与实践", 機械工業出版社，2006