Research Topics
Topic 1: Deep Neural Network Design Automation
In this project we will explore 1) DNN compression / acceleration and 2) DNN design space exploration.
Selected recent publications:
[C114] Qi Sun, Tinghuan Chen, Siting Liu, Jin Miao, Jianli Chen, Hao Yu, Bei Yu,
“Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design”,
IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Feb. 01–05, 2021.
(paper)
(slides)
(Best Paper Award Nomination)
[C113] Qi Sun, Chen Bai, Hao Geng, Bei Yu,
“Deep Neural Network Hardware Deployment Optimization via Advanced Active Learning”,
IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Feb. 01–05, 2021.
(paper)
(slides)
[C91] Yuzhe Ma, Ran Chen, Wei Li, Fanhua Shang, Wenjian Yu, Minsik Cho, Bei Yu,
“A Unified Approximation Framework for Compressing and Accelerating Deep Neural Networks”,
IEEE International Conference on Tools with Artificial Intelligence (ICTAI), Portland, OR, Nov. 4–6, 2019.
(paper)
(slides)
(Best Student Paper Award)
[J36] Qianru Zhang, Meng Zhang, Tinghuan Chen, Zhifei Sun, Yuzhe Ma, Bei Yu,
“Recent Advances in Convolutional Neural Network Acceleration”,
Neurocomputing, vol. 323, pp. 37–51, Jan., 2019.
(paper)
Topic 2: Deep Mask Learning
Selected recent publications:
[C104] Guojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, Bei Yu,
“DAMO: Deep Agile Mask Optimization for Full Chip Scale”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2–5, 2020.
(paper)
(slides)
(whova)
[C76] Hao Geng, Haoyu Yang, Yuzhe Ma, Joydeep Mitra, Bei Yu,
“SRAF Insertion via Supervised Dictionary Learning”,
IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), pp. 406–411, Tokyo, Jan. 21–24, 2019.
(paper)
(slides)
(Best Paper Award Nomination)
[C73] Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young,
“GAN-OPC: Mask Optimization with Lithography-guided Generative Adversarial Nets”,
ACM/IEEE Design Automation Conference (DAC), pp. 131:1–131:6, San Francisco, CA, June 24–28, 2018.
(paper)
(slides)
(poster)
[J39] Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young,
“Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 6, pp. 1175–1187, 2019.
(paper)
(code)
[C57] Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu,
“Bilinear Lithography Hotspot Detection”,
ACM International Symposium on Physical Design (ISPD), pp. 7–14, Portland, OR, Mar. 19–22, 2017.
(paper)
(Best Paper Award)
[C9] Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan,
“EPIC: Efficient Prediction of IC Manufacturing Hotspots With A Unified Meta-Classification Formulation”,
IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 263–270, Sydney, Australia, Jan. 30–Feb. 3, 2012.
(paper)
(Best Paper Award)
Topic 3: Learning on Chips
Machine learning is a powerful computer science technique which can derive knowledge from big data, and provides prediction and matching.
Since nanometer VLSI CAD problems have extremely high complexity and gigantic data,
there has been a surge recently in applying and adapting machine learning techniques in VLSI CAD.
Selected recent publications:
[C101] Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong,
“Learn to Floorplan through Acquisition of Effective Local Search Heuristics”,
IEEE International Conference on Computer Design (ICCD), Oct. 18–21, 2020.
(paper)
(slides)
[C98] Wei Li, Jialu Xia, Yuzhe Ma, Jialu Li, Yibo Lin, Bei Yu,
“Adaptive Layout Decomposition with Graph Embedding Neural Networks”,
ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19–23, 2020.
(paper)
(slides)
[C85] Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu,
“High Performance Graph Convolutional Networks with Applications in Testability Analysis”,
ACM/IEEE Design Automation Conference (DAC), pp. 18:1–18:6, Las Vegas, NV, June 2–6, 2019.
(paper)
(slides)
(poster)
[J43] Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu,
“Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 12, pp. 2298–2311, 2019.
(paper)
Topic 4: Hardware Friendly Computer Vision
[C100] Wanli Chen, Xinge Zhu, Ruoqi Sun, Junjun He, Ruiyu Li, Xiaoyong Shen, Bei Yu,
“Tensor Low-Rank Reconstruction for Semantic Segmentation”,
European Conference on Computer Vision (ECCV), August 23–28, 2020.
(paper)
(slides)
(code)
[C96] Husheng Zhou, Wei Li, Zelun Kong, Junfeng Guo, Yuqun Zhang, Bei Yu, Lingming Zhang, Cong Liu,
“DeepBillboard: Systematic Physical-World Testing of Autonomous Driving Systems”,
ACM/IEEE International Conference on Software Engineering (ICSE), Seoul, May 23–29, 2020.
(paper)
Topic 5: Combinatorial Algorithms in VLSI CAD
Many classical VLSI CAD problems can be extracted and formulated into challenging combinatorial optimization problems.
We are heavily working to improve the state-of-the-art.
Selected recent publications are listed as follows:
[J19] Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan,
“Stitch Aware Detailed Placement for Multiple E-Beam Lithography”,
Integration, the VLSI Journal, vol. 58, June, pp. 47–54, 2017.
(paper)
(Best Paper Award)
[C20] Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan,
“Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 349–356, San Jose, CA, Nov. 18–21, 2013.
(paper)
(slides)
(William J. McCalla Best Paper Award)
[C43] Yibo Lin, Xiaoqing Xu, Bei Yu, Ross Baldick, David Z. Pan,
“Triple/Quadruple Patterning Layout Decomposition via Novel Linear Programming and Iterative Rounding”,
SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 21–25, 2016.
(paper)
(slides)
(Best Student Paper Award)
[C7] Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan,
“Triple Patterning Lithography Layout Decomposition”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–8, San Jose, CA, Nov. 2011.
(paper)
(poster)
(slides)
(William J. McCalla Best Paper Award Nomination)
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