\hypertarget{coll__sm__barrier_8c}{\section{ompi/mca/coll/sm/coll\+\_\+sm\+\_\+barrier.c File Reference}
\label{coll__sm__barrier_8c}\index{ompi/mca/coll/sm/coll\+\_\+sm\+\_\+barrier.\+c@{ompi/mca/coll/sm/coll\+\_\+sm\+\_\+barrier.\+c}}
}
{\ttfamily \#include \char`\"{}ompi\+\_\+config.\+h\char`\"{}}\\*
{\ttfamily \#include \char`\"{}ompi/constants.\+h\char`\"{}}\\*
{\ttfamily \#include \char`\"{}ompi/communicator/communicator.\+h\char`\"{}}\\*
{\ttfamily \#include \char`\"{}ompi/mca/coll/coll.\+h\char`\"{}}\\*
{\ttfamily \#include \char`\"{}opal/sys/atomic.\+h\char`\"{}}\\*
{\ttfamily \#include \char`\"{}coll\+\_\+sm.\+h\char`\"{}}\\*
\subsection*{Functions}
\begin{DoxyCompactItemize}
\item 
int \hyperlink{coll__sm__barrier_8c_a3b9624c11ecd4f439f9712ac6361ce4c}{mca\+\_\+coll\+\_\+sm\+\_\+barrier\+\_\+intra} (struct \hyperlink{structompi__communicator__t}{ompi\+\_\+communicator\+\_\+t} $\ast$comm, \hyperlink{coll_8h_aa26d67e9c1a6d83345102a7ef73ea7d1}{mca\+\_\+coll\+\_\+base\+\_\+module\+\_\+t} $\ast$module)
\begin{DoxyCompactList}\small\item\em Shared memory barrier. \end{DoxyCompactList}\end{DoxyCompactItemize}


\subsection{Function Documentation}
\hypertarget{coll__sm__barrier_8c_a3b9624c11ecd4f439f9712ac6361ce4c}{\index{coll\+\_\+sm\+\_\+barrier.\+c@{coll\+\_\+sm\+\_\+barrier.\+c}!mca\+\_\+coll\+\_\+sm\+\_\+barrier\+\_\+intra@{mca\+\_\+coll\+\_\+sm\+\_\+barrier\+\_\+intra}}
\index{mca\+\_\+coll\+\_\+sm\+\_\+barrier\+\_\+intra@{mca\+\_\+coll\+\_\+sm\+\_\+barrier\+\_\+intra}!coll\+\_\+sm\+\_\+barrier.\+c@{coll\+\_\+sm\+\_\+barrier.\+c}}
\subsubsection[{mca\+\_\+coll\+\_\+sm\+\_\+barrier\+\_\+intra}]{\setlength{\rightskip}{0pt plus 5cm}int mca\+\_\+coll\+\_\+sm\+\_\+barrier\+\_\+intra (
\begin{DoxyParamCaption}
\item[{struct {\bf ompi\+\_\+communicator\+\_\+t} $\ast$}]{comm, }
\item[{{\bf mca\+\_\+coll\+\_\+base\+\_\+module\+\_\+t} $\ast$}]{module}
\end{DoxyParamCaption}
)}}\label{coll__sm__barrier_8c_a3b9624c11ecd4f439f9712ac6361ce4c}


Shared memory barrier. 

Tree-\/based algorithm for a barrier\+: a fan in to rank 0 followed by a fan out using the barrier segments in the shared memory area.

There are 2 sets of barrier buffers -- since there can only be, at most, 2 outstanding barriers at any time, there is no need for more than this. The generalized in-\/use flags, control, and data segments are not used.

The general algorithm is for a given process to wait for its N children to fan in by monitoring a uint32\+\_\+t in its barrier \char`\"{}in\char`\"{} buffer. When this value reaches N (i.\+e., each of the children have atomically incremented the value), then the process atomically increases the uint32\+\_\+t in its parent's \char`\"{}in\char`\"{} buffer. Then the process waits for the parent to set a \char`\"{}1\char`\"{} in the process' \char`\"{}out\char`\"{} buffer. Once this happens, the process writes a \char`\"{}1\char`\"{} in each of its children's \char`\"{}out\char`\"{} buffers, and returns.

There's corner cases, of course, such as the root that has no parent, and the leaves that have no children. But that's the general idea. 

References mca\+\_\+coll\+\_\+sm\+\_\+component, mca\+\_\+coll\+\_\+sm\+\_\+comm\+\_\+t\+::mcb\+\_\+barrier\+\_\+control\+\_\+children, mca\+\_\+coll\+\_\+sm\+\_\+comm\+\_\+t\+::mcb\+\_\+barrier\+\_\+control\+\_\+me, mca\+\_\+coll\+\_\+sm\+\_\+comm\+\_\+t\+::mcb\+\_\+barrier\+\_\+control\+\_\+parent, mca\+\_\+coll\+\_\+sm\+\_\+comm\+\_\+t\+::mcb\+\_\+barrier\+\_\+count, mca\+\_\+coll\+\_\+sm\+\_\+comm\+\_\+t\+::mcb\+\_\+tree, mca\+\_\+coll\+\_\+sm\+\_\+tree\+\_\+node\+\_\+t\+::mcstn\+\_\+num\+\_\+children, opal\+\_\+atomic\+\_\+add, and mca\+\_\+coll\+\_\+sm\+\_\+component\+\_\+t\+::sm\+\_\+control\+\_\+size.

