Generative AI for EDA and Chip Design
Location
Speaker:
Dr. REN Haoxing
Director of Design Automation Research
NVIDIA
Abstract:
This talk explores the transformative potential of Generative AI (GenAI) techniques for EDA and Chip Design. First, we introduce the physical design scaling challenge and propose leveraging GenAI to meet this challenge, particularly in core areas of physical design such as gate sizing and buffering. Using GenAI, we have achieved speed-ups that are multiple orders of magnitude faster than existing commercial tools. Additionally, we delve into the challenges associated with training and inference in GenAI models. To facilitate this, we introduce CircuitOps, an open-source tool that efficiently gathers and processes EDA data for the training and inference phases of GenAI models. Secondly, we explore the application of Large Language Models (a key GenAI technology) to improve industrial chip design productivity. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we trained domain-adapted LLMs (ChipNeMo) with internal design documents and source code. We evaluated ChipNeMo on three selected LLM applications for chip design: an engineering assistant chatbot, EDA script generation, and bug summarization and analysis. Our results show that domain adaptation techniques enable significant LLM performance improvements over general-purpose base models. We also find that domain adaptation is orthogonal to retrieval augmented generation (RAG). On the engineering assistant application, our best model achieved 20% higher performance than GPT-4 with RAG.
Biography:
Haoxing Ren (Mark) serves as the Director of Design Automation Research at NVIDIA, where he focuses on leveraging machine learning and GPU-accelerated tools to enhance chip design quality and productivity. Prior to joining NVIDIA in 2016, he dedicated 15 years to EDA algorithm research and design methodology innovation at IBM Microelectronics and IBM Research. Mark is widely recognized for his contributions to physical design, AI, and GPU acceleration for EDA, achievements that have earned him several prestigious awards, including the IBM Corporate Award and best paper awards at ISPD, DAC, TCAD, and MLCAD. He holds over twenty patents and has co-authored over 100 papers and books including a book on ML for EDA and several book chapters in physical design and logic synthesis. He holds Bachelor’s and Master’s degrees from Shanghai Jiao Tong University and Rensselaer Polytechnic Institute, respectively, and earned his PhD from the University of Texas at Austin. He is a Fellow of the IEEE.
Enquiries: Mr. WONG O-Bong (obong@cse.cuhk.edu.hk)