Objective

Syllabus
This course deals with methodologies to design VLSI circuits for DSP algorithms used in a wide range of signal processing applications. Architectural techniques to optimize for speed, power consumption or size include pipelining, retiming, unfolding, folding and systolic array. The course also introduces a hardware description language(HDL), and shows the example of using HDL to design a signal processing system. Practical work will be arranged for students to gain first hand experience of designing and implementing DSP algorithms.

Learning Outcome

1. Use signal diagram to describe digital signal processing algorithms
2. Understand different architectural transforms to optimize a VLSI DSP circuit for speed, power consumption or size.
3. Understand a Hardware Description Language and has the ability to use the HDL to design VLSI DSP circuits
4. Gain the experience of using FPGA Design Tools

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