Congratulations to Siting LIU (a PhD student supervised by Prof. Bei Yu and Prof. Martin Wong) and co-authors (Peiyu Liao, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin and Bei Yu) won DATE Best Paper Award (D Track) at the ACM/IEEE Design, Automation and Test in Europe Conference (DATE 2022) for their paper “FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler”.
DATE Best Paper Award is to recognize the best paper presented at DATE. The awards are split into four tracks, Track D: Design Methods and Tools; Track A: Application Design; Track T: Test and Dependability; Track E: Embedded Systems Design. Track D addresses design automation, design tools and hardware architectures for electronic and embedded systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments. The awards are decided by DATE Best Paper Awards Selection Committees.
Abstract:
Routing is an essential step to integrated circuits (IC) design closure. With the rapid increase of design scales, routing has become the runtime bottleneck in the physical design flow. Thus, accelerating routing becomes a vital and ur-gent task for IC design automation. This paper proposes a global routing framework running on hybrid CPU-GPU platforms with a heterogeneous task scheduler and a GPU-accelerated pattern routing algorithm. We demonstrate that the task scheduler can lead to 2.307x speedup compared with the widely-adopted batch-based parallelization strategy on CPU and the GPU-accelerated pattern routing algorithm can contribute to 10.877x speedup over the sequential algorithm on CPU. Finally, the combined techniques can achieve 2.426x speedup without quality degradation compared with the state-of-the-art global router.
