20 #ifndef OMPI_SYS_ARCH_ATOMIC_H
21 #define OMPI_SYS_ARCH_ATOMIC_H 1
29 #if OPAL_WANT_SMP_LOCKS
30 #define MEMBAR(type) __asm__ __volatile__ ("membar " type : : : "memory")
41 #define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
43 #define OPAL_HAVE_ATOMIC_CMPSET_32 1
45 #define OPAL_HAVE_ATOMIC_CMPSET_64 1
53 #if OMPI_GCC_INLINE_ASSEMBLY
57 MEMBAR(
"#LoadLoad | #LoadStore | #StoreStore | #StoreLoad");
69 MEMBAR(
"#StoreStore");
80 #if OMPI_GCC_INLINE_ASSEMBLY
82 static inline int opal_atomic_cmpset_32(
volatile int32_t *addr,
83 int32_t oldval, int32_t newval)
95 __asm__ __volatile__(
"casa [%1] " ASI_P
", %2, %0"
97 :
"r" (addr),
"r" (oldval));
98 return (ret == oldval);
102 static inline int opal_atomic_cmpset_acq_32(
volatile int32_t *addr,
103 int32_t oldval, int32_t newval)
107 rc = opal_atomic_cmpset_32(addr, oldval, newval);
114 static inline int opal_atomic_cmpset_rel_32(
volatile int32_t *addr,
115 int32_t oldval, int32_t newval)
118 return opal_atomic_cmpset_32(addr, oldval, newval);
122 #if OPAL_ASSEMBLY_ARCH == OMPI_SPARCV9_64
124 static inline int opal_atomic_cmpset_64(
volatile int64_t *addr,
125 int64_t oldval, int64_t newval)
134 int64_t ret = newval;
136 __asm__ __volatile__(
"casxa [%1] " ASI_P
", %2, %0"
138 :
"r" (addr),
"r" (oldval));
139 return (ret == oldval);
144 static inline int opal_atomic_cmpset_64(
volatile int64_t *addr,
145 int64_t oldval, int64_t newval)
155 long long ret = newval;
157 __asm__ __volatile__(
160 "casxa [%1] " ASI_P
", %%g2, %%g1 \n\t"
163 :
"r"(addr),
"m"(oldval)
167 return (ret == oldval);
172 static inline int opal_atomic_cmpset_acq_64(
volatile int64_t *addr,
173 int64_t oldval, int64_t newval)
177 rc = opal_atomic_cmpset_64(addr, oldval, newval);
184 static inline int opal_atomic_cmpset_rel_64(
volatile int64_t *addr,
185 int64_t oldval, int64_t newval)
188 return opal_atomic_cmpset_64(addr, oldval, newval);
void opal_atomic_rmb(void)
Read memory barrier.
void opal_atomic_mb(void)
Memory barrier.
void opal_atomic_wmb(void)
Write memory barrier.