19 #ifndef OMPI_SYS_ARCH_ATOMIC_H
20 #define OMPI_SYS_ARCH_ATOMIC_H 1
26 #if OPAL_WANT_SMP_LOCKS
28 #define MB() __asm__ __volatile__ ("mb");
29 #define RMB() __asm__ __volatile__ ("mb");
30 #define WMB() __asm__ __volatile__ ("wmb");
46 #define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
48 #define OPAL_HAVE_ATOMIC_CMPSET_32 1
50 #define OPAL_HAVE_ATOMIC_CMPSET_64 1
58 #if OMPI_GCC_INLINE_ASSEMBLY
85 #if OMPI_GCC_INLINE_ASSEMBLY
87 static inline int opal_atomic_cmpset_32(
volatile int32_t *addr,
88 int32_t oldval, int32_t newval)
93 "1: ldl_l %0, %1 \n\t"
94 "cmpeq %0, %2, %0 \n\t"
102 :
"=&r" (ret),
"+m" (*addr)
103 :
"r" (oldval),
"r" (newval)
110 static inline int opal_atomic_cmpset_acq_32(
volatile int32_t *addr,
116 rc = opal_atomic_cmpset_32(addr, oldval, newval);
123 static inline int opal_atomic_cmpset_rel_32(
volatile int32_t *addr,
128 return opal_atomic_cmpset_32(addr, oldval, newval);
132 static inline int opal_atomic_cmpset_64(
volatile int64_t *addr,
133 int64_t oldval, int64_t newval)
137 __asm__ __volatile__ (
138 "1: ldq_l %0, %1 \n\t"
139 "cmpeq %0, %2, %0 \n\t"
147 :
"=&r" (ret),
"+m" (*addr)
148 :
"r" (oldval),
"r" (newval)
155 static inline int opal_atomic_cmpset_acq_64(
volatile int64_t *addr,
161 rc = opal_atomic_cmpset_64(addr, oldval, newval);
168 static inline int opal_atomic_cmpset_rel_64(
volatile int64_t *addr,
173 return opal_atomic_cmpset_64(addr, oldval, newval);
void opal_atomic_rmb(void)
Read memory barrier.
void opal_atomic_mb(void)
Memory barrier.
void opal_atomic_wmb(void)
Write memory barrier.