19 #ifndef OMPI_SYS_ARCH_ATOMIC_H
20 #define OMPI_SYS_ARCH_ATOMIC_H 1
27 #if OPAL_WANT_SMP_LOCKS
28 #define SMPLOCK "lock; "
29 #define MB() __asm__ __volatile__("": : :"memory")
41 #define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
43 #define OPAL_HAVE_ATOMIC_CMPSET_32 1
45 #define OPAL_HAVE_ATOMIC_CMPSET_64 1
47 #define OPAL_HAVE_ATOMIC_SWAP_32 1
49 #define OPAL_HAVE_ATOMIC_SWAP_64 1
56 #if OMPI_GCC_INLINE_ASSEMBLY
83 #if OMPI_GCC_INLINE_ASSEMBLY
85 static inline int opal_atomic_cmpset_32(
volatile int32_t *addr,
86 int32_t oldval, int32_t newval)
89 __asm__ __volatile__ (
90 SMPLOCK
"cmpxchgl %3,%2 \n\t"
92 :
"=qm" (ret),
"+a" (oldval),
"+m" (*addr)
101 #define opal_atomic_cmpset_acq_32 opal_atomic_cmpset_32
102 #define opal_atomic_cmpset_rel_32 opal_atomic_cmpset_32
104 #if OMPI_GCC_INLINE_ASSEMBLY
106 static inline int opal_atomic_cmpset_64(
volatile int64_t *addr,
107 int64_t oldval, int64_t newval)
110 __asm__ __volatile__ (
111 SMPLOCK
"cmpxchgq %3,%2 \n\t"
113 :
"=qm" (ret),
"+a" (oldval),
"+m" (*((
volatile long*)addr))
123 #define opal_atomic_cmpset_acq_64 opal_atomic_cmpset_64
124 #define opal_atomic_cmpset_rel_64 opal_atomic_cmpset_64
126 #if OMPI_GCC_INLINE_ASSEMBLY
128 static inline int32_t opal_atomic_swap_32(
volatile int32_t *addr,
133 __asm__ __volatile__(
"xchg %1, %0" :
134 "=r" (oldval),
"=m" (*addr) :
135 "0" (newval),
"m" (*addr) :
142 #if OMPI_GCC_INLINE_ASSEMBLY
144 static inline int64_t opal_atomic_swap_64(
volatile int64_t *addr,
149 __asm__ __volatile__(
"xchgq %1, %0" :
151 "m" (*addr),
"0" (newval) :
160 #if OMPI_GCC_INLINE_ASSEMBLY
162 #define OPAL_HAVE_ATOMIC_MATH_32 1
163 #define OPAL_HAVE_ATOMIC_MATH_64 1
165 #define OPAL_HAVE_ATOMIC_ADD_32 1
174 static inline int32_t opal_atomic_add_32(
volatile int32_t* v,
int i)
177 __asm__ __volatile__(
178 SMPLOCK
"xaddl %1,%0"
179 :
"=m" (*v),
"+r" (ret)
186 #define OPAL_HAVE_ATOMIC_ADD_64 1
195 static inline int64_t opal_atomic_add_64(
volatile int64_t* v, int64_t i)
198 __asm__ __volatile__(
199 SMPLOCK
"xaddq %1,%0"
200 :
"=m" (*v),
"+r" (ret)
207 #define OPAL_HAVE_ATOMIC_SUB_32 1
216 static inline int32_t opal_atomic_sub_32(
volatile int32_t* v,
int i)
219 __asm__ __volatile__(
220 SMPLOCK
"xaddl %1,%0"
221 :
"=m" (*v),
"+r" (ret)
228 #define OPAL_HAVE_ATOMIC_SUB_64 1
237 static inline int64_t opal_atomic_sub_64(
volatile int64_t* v, int64_t i)
240 __asm__ __volatile__(
241 SMPLOCK
"xaddq %1,%0"
242 :
"=m" (*v),
"+r" (ret)
void opal_atomic_rmb(void)
Read memory barrier.
void opal_atomic_mb(void)
Memory barrier.
void opal_atomic_wmb(void)
Write memory barrier.